Implementation of a Single FFT Processor
نویسنده
چکیده
This document describes a FPGA implementation and simulation of the FFT component of the IIP Radiometer RFI processor described in [1]. A possible implementation of this FFT component has been previously described in [2]. Here a single FFT processor will be implemented and tested before proceeding to a larger design consisting of many such processors. This document is broken into three separate sections. The first section presents simulations of the Altera FFT Megacore, with special emphasis on its floating point outputs. Secondly, synthesis results for an Altera EP20K100EQC208-1 FPGA will be presented. Finally, implementation results of the FFT processor will be illustrated.
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